US 12,067,254 B2
Low latency SSD read architecture with multi-level error correction codes (ECC)
Zongwang Li, Dublin, CA (US); Jing Yang, San Jose, CA (US); Marie Mai Nguyen, Pittsburg, PA (US); Mehran Elyasi, Saint Paul, MN (US); and Rekha Pitchumani, Oak Hill, VA (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Mar. 14, 2022, as Appl. No. 17/694,657.
Claims priority of provisional application 63/302,023, filed on Jan. 21, 2022.
Claims priority of provisional application 63/191,916, filed on May 21, 2021.
Prior Publication US 2022/0374152 A1, Nov. 24, 2022
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A storage unit, comprising:
a storage for a component codeword, the component codeword stored in a block of a first size in the storage, the block further storing a block codeword;
an interface to receive a read request for a chunk of data of a second size from a host and to send the chunk of data to the host, the second size smaller than the first size;
a circuit to read the component codeword from the block in the storage;
an error correcting code (ECC) decoder to determine the chunk of data based at least in part on the component codeword.