US 12,067,245 B2
Memory controller and method of operating the same
Seon Ju Lee, Gyeonggi-do (KR); Seung Geol Baek, Gyeonggi-do (KR); Jae Hyun Yoo, Gyeonggi-do (KR); and Dong Kyu Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Dec. 14, 2022, as Appl. No. 18/081,605.
Claims priority of application No. 10-2022-0066799 (KR), filed on May 31, 2022.
Prior Publication US 2023/0384937 A1, Nov. 30, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0611 (2013.01) [G06F 3/0653 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
13. A method of operating a memory controller, the method comprising:
counting an over-latency count value representing a number of over-latencies exceeding a reference value among latencies for requests of a host during each of a plurality of periods;
calculating gaps which are difference values between the over-latency count values of the plurality of periods;
generating latency information including the over-latency count values and the gaps;
determining, based on the latency information, whether each gap corresponding to at least two target periods among the plurality of periods exceeds a threshold value; and
delaying a response to the requests according to a result of the determining.