US 12,067,240 B2
Flash memory scheme capable of automatically generating or removing dummy data portion of full page data by using flash memory device
Tsu-Han Lu, Hsinchu (TW); and Hsiao-Chang Yen, Hsinchu County (TW)
Assigned to Silicon Motion, Inc., Hsinchu County (TW)
Filed by Silicon Motion, Inc., Hsinchu County (TW)
Filed on Sep. 30, 2022, as Appl. No. 17/956,855.
Prior Publication US 2024/0111417 A1, Apr. 4, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0658 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface, comprising:
an input/output (I/O) circuit, coupled to the flash memory device through the specific communication interface, for sending commands and data between the flash memory device and a processor; and
the processor, coupled to the I/O circuit, for controlling the I/O circuit using a set-feature signal, which carries a set-feature command, a feature address, and corresponding parameter information, and transmitting the set-feature signal to the flash memory device;
wherein the feature address corresponds to a valid data portion or a dummy data portion following the valid data portion, and both the valid data potion and the dummy data portion are comprised in a full page data which is to be written into a physical page unit of the flash memory device or is to be read out from the physical page unit; the corresponding parameter information is used to record the valid data portion's column address and data length, the dummy data portion's column address and data length, the dummy data portion's column address and the valid data portion's column address, or the dummy data portion's data length and the valid data portion's data length.