CPC G06F 21/14 (2013.01) [G06F 21/73 (2013.01)] | 17 Claims |
1. A method, comprising: performing a capture operation that loads a plurality of primary input (PI) values into corresponding shift registers of a plurality of test data registers (TDRs) disposed on one or more digital semiconductor devices and configured to store a plurality of secret information bits; performing a sequence of shift operations on the plurality of TDRs to obtain a plurality of output bits; and applying, by a processor, a derivation function on the plurality of output bits to extract the plurality of secret information bits thereby authenticating the one or more digital semiconductor devices, wherein a PI value from the plurality of PI values of a first TDR of the plurality of TDRs is set to a logic high or a logic low based at least in part on the plurality of secret information bits.
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