US 12,066,958 B2
Clock generation for timing communications with ranks of memory devices
Jared L. Zerbe, Woodside, CA (US); Ian P. Shaeffer, Los Gatos, CA (US); and John Eble, Chapel Hill, CA (US)
Assigned to RAMBUS INC., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Apr. 14, 2023, as Appl. No. 18/135,095.
Application 18/135,095 is a continuation of application No. 16/921,061, filed on Jul. 6, 2020, granted, now 11,630,788.
Application 16/921,061 is a continuation of application No. 16/228,695, filed on Dec. 20, 2018, granted, now 10,705,990, issued on Jul. 7, 2020.
Application 16/228,695 is a continuation of application No. 15/424,714, filed on Feb. 3, 2017, granted, now 10,162,772, issued on Dec. 25, 2018.
Application 15/424,714 is a continuation of application No. 14/954,940, filed on Nov. 30, 2015, granted, now 9,563,228, issued on Feb. 7, 2017.
Application 14/954,940 is a continuation of application No. 13/990,370, granted, now 9,201,444, issued on Dec. 1, 2015, previously published as PCT/US2011/059851, filed on Nov. 9, 2011.
Claims priority of provisional application 61/417,845, filed on Nov. 29, 2010.
Prior Publication US 2023/0359572 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01); G06F 1/04 (2006.01); G06F 1/06 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); G11C 7/22 (2006.01); G11C 7/04 (2006.01); H04L 7/033 (2006.01)
CPC G06F 13/1689 (2013.01) [G06F 1/04 (2013.01); G06F 1/06 (2013.01); G06F 1/08 (2013.01); G06F 1/10 (2013.01); G06F 13/161 (2013.01); G06F 13/1657 (2013.01); G11C 7/222 (2013.01); G11C 7/04 (2013.01); H04L 7/033 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller to control the operation of first and second memory devices configured as respective first and second ranks, the memory controller comprising:
a strobe receiver circuit to receive, via a strobe signal line:
a first strobe signal from the first memory device, wherein the first memory device is configured in a first rank of memory; and
a second strobe signal from the second memory device, wherein the second memory device is configured in a second rank of memory;
a calibration circuit operable in a calibration mode to generate rank specific calibration data for the first memory device and the second memory device, the calibration data including:
first calibration data based on the first strobe signal received from the first memory device via the strobe signal line; and
second calibration data based on the second strobe signal received from the second memory device via the strobe signal line;
and
a data sampling circuit, to receive:
first read data in association with read operations from the first memory device, the first read data to be received using an adjusted sampling phase based on the first calibration data; and
second read data in association with read operations from the second memory device, the second read data to be received using an adjusted sampling phase based on the second calibration data.