US 12,066,954 B2
Methods, apparatus, and systems for secure demand paging and paging operations for processor devices
Steven C. Goss, Addison, TX (US); Gregory Remy Philippe Conti, St Paul (FR); Narendar M. Shankar, San Jose, CA (US); Mehdi-Laurent Akkar, Paris (FR); and Aymeric Vial, Antibes (FR)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Nov. 30, 2020, as Appl. No. 17/106,372.
Application 14/457,800 is a division of application No. 13/345,484, filed on Jan. 6, 2012, granted, now 8,812,804, issued on Aug. 19, 2014.
Application 13/345,484 is a division of application No. 11/426,597, filed on Jun. 27, 2006, granted, now 8,108,641, issued on Jan. 31, 2012.
Application 17/106,372 is a continuation of application No. 15/097,935, filed on Apr. 13, 2016, granted, now 10,853,269.
Application 15/097,935 is a continuation of application No. 14/457,800, filed on Aug. 12, 2014, granted, now 9,432,196, issued on Aug. 30, 2016.
Prior Publication US 2021/0240637 A1, Aug. 5, 2021
Int. Cl. G06F 12/14 (2006.01); G06F 9/455 (2018.01); G06F 9/46 (2006.01); G06F 12/02 (2006.01); G06F 21/57 (2013.01); G06F 21/79 (2013.01); H04L 9/08 (2006.01); H04L 9/32 (2006.01); H04L 9/40 (2022.01); H04W 12/069 (2021.01); H04W 12/102 (2021.01); G06F 12/08 (2016.01)
CPC G06F 12/1408 (2013.01) [G06F 9/45558 (2013.01); G06F 9/461 (2013.01); G06F 12/0246 (2013.01); G06F 12/145 (2013.01); G06F 12/1483 (2013.01); G06F 21/575 (2013.01); G06F 21/79 (2013.01); H04L 9/0897 (2013.01); H04L 9/3236 (2013.01); H04L 63/18 (2013.01); H04L 63/20 (2013.01); H04W 12/069 (2021.01); H04W 12/102 (2021.01); G06F 2009/45583 (2013.01); G06F 2009/45587 (2013.01); G06F 12/08 (2013.01); G06F 2212/171 (2013.01); G06F 2212/402 (2013.01); G06F 2212/7201 (2013.01); H04L 63/123 (2013.01); Y02D 10/00 (2018.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
an internal memory that includes a page slot, wherein the internal memory is configured to be a secure memory;
an external memory; and
a processor coupled to the internal memory and to the external memory, the processor configured to:
wipe a first page from the page slot of the internal memory;
read a second page from the external memory;
perform a first hash operation on the second page to determine a first hash value;
compare the first hash value to a first predetermined hash value;
decrypt the second page to produce a decrypted page;
store the decrypted page in the page slot;
read the decrypted page from the page slot;
perform a second hash operation on the decrypted page as read from the page slot to determine a second hash value;
compare the second hash value to a second predetermined hash value; and
in response to the second hash value not matching the second predetermined hash value, wipe the decrypted page from the page slot of the internal memory.