US 12,066,948 B2
Dynamic banking and bit separation in memories
Russell J. Schreiber, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Mar. 21, 2022, as Appl. No. 17/699,401.
Application 17/699,401 is a continuation of application No. 16/680,491, filed on Nov. 11, 2019, granted, now 11,281,592.
Prior Publication US 2022/0206948 A1, Jun. 30, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/08 (2016.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01); G06F 12/0877 (2016.01); G11C 7/10 (2006.01); G11C 8/12 (2006.01)
CPC G06F 12/0877 (2013.01) [G06F 12/0246 (2013.01); G06F 12/0661 (2013.01); G11C 7/1045 (2013.01); G11C 8/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system configurable to operate in either a banked mode or a bit-separated mode, the system comprising:
a plurality of memory banks;
multiplexing circuitry; and
input circuitry configured to input at least a portion of a memory address to the multiplexing circuitry, and to input configuration information to the multiplexing circuitry;
the multiplexing circuitry configured to, if the configuration information indicates a bit-separated mode: generate read data by combining a selected subset of data corresponding to the memory address from each of the plurality of memory banks, the subset selected based on the configuration information;
the multiplexing circuitry further configured to, if the configuration information indicates a banked mode: generate the read data by combining data corresponding to the memory address from one of the memory banks, the one of the memory banks selected based on the configuration information; and output circuitry configured to output the generated read data.