US 12,066,946 B2
Methods and apparatuses for dynamically changing data priority in a cache
Xiaodong Qiu, Shanghai (CN); Yong Jiang, Shanghai (CN); Changwon Rhee, Rocklin, CA (US); Cui Tang, Beijing (CN); Shuangpeng Zhou, Shanghai (CN); Lei Chen, Shanghai (CN); Danyu Bi, Shanghai (CN); Peiqing Jiang, Shanghai (CN); and Chengxi Wu, Shanghai (CN)
Assigned to INTEL CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 25, 2022, as Appl. No. 17/704,340.
Claims priority of application No. 202110714268.1 (CN), filed on Jun. 25, 2021.
Prior Publication US 2022/0414010 A1, Dec. 29, 2022
Int. Cl. G06F 12/084 (2016.01); G06F 9/48 (2006.01)
CPC G06F 12/084 (2013.01) [G06F 9/4818 (2013.01); G06F 2212/604 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus comprising:
processor circuitry to host priority controller circuitry, the processor circuitry to:
receive a memory access request to request data; and
set a priority flag for the memory access request based on an amount of data associated with a memory block to be accessed using the memory access request, wherein the priority flag indicates a priority level associated with the memory access request in accessing the amount of data, wherein the priority flag is set based on the amount to be accessed with respect to a threshold access amount for the memory block.