US 12,066,941 B2
Method for executing atomic memory operations when contested
John Ingalls, Sunnyvale, CA (US); Wesley Waylon Terpstra, San Mateo, CA (US); Henry Cook, Berkeley, CA (US); and Leigang Kou, Austin, TX (US)
Assigned to SiFive, Inc., San Mateo, CA (US)
Filed by SiFive, Inc., San Mateo, CA (US)
Filed on Oct. 6, 2022, as Appl. No. 17/961,146.
Application 17/961,146 is a continuation of application No. 17/009,876, filed on Sep. 2, 2020, granted, now 11,467,962.
Prior Publication US 2023/0033550 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/08 (2016.01); G01N 29/24 (2006.01); G06F 12/0811 (2016.01); G06F 12/0813 (2016.01); G06F 12/0846 (2016.01); G06F 12/0891 (2016.01); G06F 12/123 (2016.01); H01S 5/042 (2006.01); H01S 5/06 (2006.01); H01S 5/10 (2021.01)
CPC G06F 12/0811 (2013.01) [G01N 29/2418 (2013.01); G06F 12/0813 (2013.01); G06F 12/0846 (2013.01); G06F 12/0891 (2013.01); G06F 12/123 (2013.01); H01S 5/0427 (2013.01); H01S 5/0612 (2013.01); H01S 5/1042 (2013.01); H01S 5/1096 (2013.01); G06F 2212/1021 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processing system comprising:
at least two cores, each core having a local cache;
a lower level cache in communication with both local caches;
one local cache configured to:
request a cache line to execute an atomic memory operation (AMO) instruction;
receive the cache line via the lower level cache, wherein the lower level cache is configured to determine availability of the cache line based on input from other caches or memory structures associated with the cache line;
receive a probe downgrade due to a remaining local cache requesting the requested cache line prior to execution of the AMO; and
send the AMO instruction to the lower level cache for remote execution in response to the probe downgrade.