US 12,066,940 B2
Data reuse cache
Alok Garg, Maynard, MA (US); Neil N Marketkar, Jamaica Plain, MA (US); and Matthew T. Sobel, Boxborough, MA (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Sep. 29, 2022, as Appl. No. 17/955,618.
Prior Publication US 2024/0111674 A1, Apr. 4, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 12/0811 (2016.01); G06F 12/0875 (2016.01); G06F 12/0884 (2016.01)
CPC G06F 12/0811 (2013.01) [G06F 12/0875 (2013.01); G06F 12/0884 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
generating a load instruction at an execution unit;
in response to the load instruction:
loading data from a load response obtained from a load-store unit for processing by the execution unit; and
storing the data from the load response to a data reuse cache communicatively coupled between the load-store unit and the execution unit;
generating a subsequent load instruction for the data at the execution unit; and
loading the data from the data reuse cache for processing by the execution unit in response to the subsequent load instruction.