US 12,066,939 B2
Cache line demote infrastructure for multi-processor pipelines
Rahul R. Shah, Chandler, AZ (US); Omkar Maslekar, Chandler, AZ (US); Priya Autee, Chandler, AZ (US); Edwin Verplanke, Chandler, AZ (US); Andrew J. Herdrich, Hillsboro, OR (US); and Jeffrey D. Chamberlain, Tracy, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 30, 2020, as Appl. No. 17/086,243.
Prior Publication US 2021/0073129 A1, Mar. 11, 2021
Int. Cl. G06F 12/00 (2006.01); G06F 9/30 (2018.01); G06F 12/0811 (2016.01); G06F 12/084 (2016.01); G06F 12/1009 (2016.01)
CPC G06F 12/0811 (2013.01) [G06F 9/30047 (2013.01); G06F 9/30079 (2013.01); G06F 12/084 (2013.01); G06F 12/1009 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method comprising:
in response to a processor caching data, associated with a region of memory addresses, into a cache and based on an indication that an entirety of the region of memory addresses is associated with a cache line demote operation, demoting content of the entirety of the region of memory addresses from the cache to a shared cache, wherein the region of memory addresses comprises a region corresponding to multiple cache lines and wherein the content of the entirety of the region of memory addresses comprises the data.