US 12,066,938 B2
Data pattern based cache management
Michael R. Seningen, Austin, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jul. 27, 2023, as Appl. No. 18/360,352.
Application 18/360,352 is a continuation of application No. 17/929,544, filed on Sep. 2, 2022, granted, now 11,755,480.
Application 17/929,544 is a continuation of application No. 17/033,587, filed on Sep. 25, 2020, granted, now 11,442,855, issued on Aug. 24, 2022.
Prior Publication US 2024/0134792 A1, Apr. 25, 2024
Prior Publication US 2024/0232077 A9, Jul. 11, 2024
Int. Cl. G06F 12/08 (2016.01); G06F 12/0802 (2016.01)
CPC G06F 12/0802 (2013.01) [G06F 2212/60 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory circuit including a plurality of memory blocks; and
a control circuit configured to:
maintain a record of a background data pattern, wherein the record is accessible outside of the memory circuit;
scan the plurality of memory blocks to identify occurrences of the background data pattern stored within the plurality of memory blocks; and
in response to identifying a particular occurrence of the background data pattern in a particular location of a first memory block of the plurality, relocate the particular location to a designated one of the plurality of memory blocks.