US 12,066,929 B2
Techniques for efficient address translation using metadata with mixed mapping schemes
Vladimir Shveidel, Pardes-Hana (IL); and Amitai Alkalay, Kadima (IL)
Assigned to Dell Products L.P., Hopkinton, MA (US)
Filed by Dell Products L.P., Hopkinton, MA (US)
Filed on Jul. 18, 2022, as Appl. No. 17/866,912.
Prior Publication US 2024/0020225 A1, Jan. 18, 2024
Int. Cl. G06F 12/02 (2006.01)
CPC G06F 12/0246 (2013.01) [G06F 2212/7201 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A computer-implemented method comprising:
performing first processing that maintains a first storage tier including a first plurality of metadata (MD pages included in a hierarchical structure, wherein said first processing includes:
determining an updated version of a first MD page of the first plurality of MD pages, wherein an existing version of the first MD page is stored at a first storage location of the first storage tier; and
storing the updated version of the first MD page at the first storage location of the first storage tier; and
performing second processing that maintains a second storage tier including a second plurality of MD pages included in the hierarchical structure, wherein said second processing includes:
determining an updated version of a second MD page of the second plurality of MD pages, wherein an existing version of the second MD page is stored at a second storage location of the second storage tier; and
storing the updated version of the second MD page at a new storage location of the second storage tier, wherein the new storage location denotes a different physical storage location than the second storage location, wherein the hierarchical structure including the first plurality of MD pages and the second plurality of MD pages is used in connection with mapping logical addresses to physical locations or addresses of content stored at the logical addresses, wherein the first plurality of MD pages includes a plurality of MD top pages and a plurality of MD mid pages, wherein the second plurality of MD pages includes a plurality of MD leaf pages, and wherein a first logical address is mapped to a first non-volatile storage location including first content stored at the first logical address, wherein the first logical address is mapped by mapping information including a first chain of MD pages of the hierarchical structure, wherein the first chain includes a first MD top page of the MD top pages, a first MD mid page of the MD mid pages, and a first MD leaf page of the MD leaf pages, wherein a first entry of the first MD top page references a second entry of the first MD mid page, and wherein the second entry references a third entry of the first MD leaf page, and wherein the first MD top page, the first MD mid page and the first MD leaf page are associated with corresponding logical address ranges including the first logical address.