US 12,066,928 B2
Memory system, memory controller and operation method thereof
Eu Joon Byun, Icheon-si (KR)
Assigned to SK HYNIX INC., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jan. 6, 2023, as Appl. No. 18/151,320.
Claims priority of application No. 10-2022-0086114 (KR), filed on Jul. 13, 2022.
Prior Publication US 2024/0020224 A1, Jan. 18, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 12/02 (2006.01); G06F 13/16 (2006.01)
CPC G06F 12/0238 (2013.01) [G06F 13/1673 (2013.01); G06F 2212/7201 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A memory controller comprising:
a first interface in communication with a first external device to perform data communication between the memory controller and the first external device;
a second interface in communication with a second external device to transmit, to the second external device, a signal for controlling an operation of the second external device;
a buffer configured to store: a first map comprising mapping information between a logical address of the first external device for storing first data which is a first type data and a physical address of the second external device where the first data is stored; and a second map comprising mapping information between a logical address of the first external device for storing second data which is a second-type data and a physical address of the second external device where the second data is stored; and
a processor configured to update the first map and the second map based on a control signal received from the first external device, and store the first map in the second external device,
wherein the first map maintains the mapping information even after a reset operation is performed, and
wherein the second map loses the mapping information after the reset operation is performed.