	US 12,066,926 B2
	Circuitry for memory address collision prevention
Andy Wangkun Chen, Austin, TX (US); Yew Keong Chong, Austin, TX (US); and Sriram Thyagarajan, Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Jul. 8, 2022, as Appl. No. 17/861,084.
Prior Publication US 2024/0012748 A1, Jan. 11, 2024
Int. Cl. G06F 12/02 (2006.01)

CPC G06F 12/023 (2013.01) [G06F 2212/1008 (2013.01)]

19 Claims

1. A circuit comprising:

comparator circuitry coupled to peripheral circuitry to a multiport memory, wherein the comparator circuitry is configured to transmit one or more data input signals or one or more write enable signals from respective inputs of the peripheral circuitry to respective memory outputs when a memory address collision is detected for one or more respective bitcells of the multi-port memory, wherein the peripheral circuitry comprises one or more data input sections, wherein:

for each data input section:

a first multiplexer is configured to receive a data input signal;

an AND gate is configured to receive a write enable signal; and

first and second latches are configured to receive the data input signal and the write enable signal and output the respective signals to an OR gate.