| CPC G06F 11/1068 (2013.01) | 20 Claims |
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1. A semiconductor memory device comprising:
a memory cell array including a plurality of volatile memory cells coupled to a plurality of word-lines and a plurality of bit-lines;
a link error correction code (ECC) engine configured to:
receive a first codeword received from a memory controller, wherein the first codeword includes main data and a first parity data; and
perform a first ECC decoding on the first codeword to generate the main data from the first codeword; and
an on-die ECC engine configured to:
receive the main data from the link ECC engine;
perform a first ECC encoding on the main data received from the link ECC engine to generate a second parity data; and
generate a second codeword including the main data and the second parity data,
wherein the on-die ECC engine, in response to a result of the first ECC decoding indicating that the first codeword includes a first type of uncorrectable errors,
generates a third codeword by changing at least one of bits of the second codeword based on a first type of error pattern associated with the first type of uncorrectable errors, and
provides the third codeword to a first target page of the memory cell array,
wherein the first type of uncorrectable errors occurs during a data transmission between the memory controller and the semiconductor memory device.
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