US 12,066,885 B2
Collection of forensic data after a processor freeze
Craig L. Chaiken, Pflugerville, TX (US); Balasingh P. Samuel, Round Rock, TX (US); and Siva Subramaniam Rajan, Austin, TX (US)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by Dell Products L.P., Round Rock, TX (US)
Filed on Jun. 16, 2022, as Appl. No. 17/841,913.
Prior Publication US 2023/0409423 A1, Dec. 21, 2023
Int. Cl. G06F 11/07 (2006.01); G06F 11/10 (2006.01); G06F 11/14 (2006.01); G06F 11/22 (2006.01); G06F 11/30 (2006.01)
CPC G06F 11/0772 (2013.01) [G06F 11/0757 (2013.01); G06F 11/0778 (2013.01); G06F 11/0787 (2013.01); G06F 11/1024 (2013.01); G06F 11/1417 (2013.01); G06F 11/1441 (2013.01); G06F 11/2236 (2013.01); G06F 11/3089 (2013.01); G06F 11/079 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An information handling system comprising:
a processor to execute operations while the information handling system is in an active power state;
an embedded controller configured to communicate with the processor, the embedded controller to:
detect a trigger event;
in response to the trigger event, provide a ping command to the processor; and
based on a response to the ping command not being received, the embedded controller to:
determine a processor freeze;
in response to the processor freeze, allocate a memory region within a basic input/output system (BIOS) memory for forensic data associated with the processor freeze;
store the forensic data associated with the processor freeze in the allocated memory region; and
store an indication to perform a processor freeze recovery during a next boot operation, wherein the next boot is a processor freeze recovery boot; and
a BIOS configured to communicate with the embedded controller and with the processor, during the processor freeze recovery boot the BIOS to:
skip an initializing of the processor; and
skip a clearing of error register statuses in the allocated memory region with the BIOS memory.