US 12,066,855 B2
Multi-port circuit architecture
Andy Wangkun Chen, Austin, TX (US); Yew Keong Chong, Austin, TX (US); Sriram Thyagarajan, Austin, TX (US); Akash Bangalore Srinivasa, Bangalore (IN); Munish Kumar, Greater Noida West (IN); Khushal Gelda, Jaipur (IN); and Akshay Kumar, New Delhi (IN)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Dec. 30, 2022, as Appl. No. 18/091,719.
Prior Publication US 2024/0219955 A1, Jul. 4, 2024
Int. Cl. G06F 1/00 (2006.01); G06F 1/06 (2006.01); G06F 1/10 (2006.01); G06F 11/30 (2006.01)
CPC G06F 1/10 (2013.01) [G06F 1/06 (2013.01); G06F 11/3062 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
multi-port circuit architecture having multiple ports,
wherein the multi-port circuit architecture expands a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit (CPU).