| CPC G06F 1/08 (2013.01) [G06F 1/3203 (2013.01); G06F 1/324 (2013.01); G06F 9/30101 (2013.01); G06F 9/45558 (2013.01); G06F 2009/45591 (2013.01); Y02D 10/00 (2018.01)] | 30 Claims |
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1. A multi-core processor comprising:
a plurality of processing cores;
a plurality of control registers, each control register of the plurality of control registers associated with a corresponding processing core;
the plurality of control registers to store a corresponding plurality of values to indicate a per-core clock frequency for corresponding processing cores, the plurality of values initially comprising a plurality of default values to indicate a default per-core clock frequency for a corresponding processing core, the plurality of default values determined during manufacture of the multi-core processor;
execution circuitry to execute software or firmware to indicate a target service level for one or more virtual machines or containers, the target service level associated with target per-core clock frequencies for one or more processing cores of the plurality of processing cores, the target per-core clock frequencies different from corresponding default per-core clock frequencies;
power management circuitry to execute power management firmware to control clock frequencies of the processing cores based, at least in part, on the plurality of values, the power management circuitry to:
receive a plurality of target values associated with the target per-core clock frequencies,
store the plurality of target values in corresponding control registers of the plurality of control registers, each target value to indicate a target per-core clock frequency for a corresponding processing core of the plurality of processing cores,
cause each corresponding processing core of the plurality of processing cores to run at the corresponding target per-core clock frequency, and
expose the plurality of target values to software.
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