US 12,066,488 B2
Embedded PHY (EPHY) IP core for FPGA
Doron Ganon, Kfar Vradim (IL); and Eitan Lerner, Karmiel (IL)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on May 16, 2023, as Appl. No. 18/197,902.
Application 18/197,902 is a division of application No. 16/805,244, filed on Feb. 28, 2020, granted, now 11,675,008.
Prior Publication US 2023/0305058 A1, Sep. 28, 2023
Int. Cl. G01R 31/28 (2006.01); G01R 31/00 (2006.01); G01R 31/3183 (2006.01); G06F 1/04 (2006.01); G06F 7/64 (2006.01); G06F 30/347 (2020.01)
CPC G01R 31/318335 (2013.01) [G01R 31/002 (2013.01); G06F 1/04 (2013.01); G06F 7/64 (2013.01); G06F 30/347 (2020.01)] 19 Claims
OG exemplary drawing
 
1. A testing device, comprising:
a field programmable gate array (FPGA); and
an embedded physical layer (EPHY), the EPHY including:
a logic portion having a first logical phy and a second logical phy, wherein the logic portion is disposed in the FPGA, and wherein the logic portion communicates with the FPGA through the first and second logical phys; and
a glue hardware portion, wherein the logic portion communicates with a device under test (DUT) through the glue hardware portion, the glue hardware portion including:
a first differential amplifier; and
a first multiplexer (MUX) coupled to the first differential amplifier and the FPGA via a first line, wherein the testing device is capable of receiving and sending signals to and from the DUT at a first speed, wherein the testing device is capable of receiving and sending signals to and from the DUT at a second speed, wherein the second speed is greater than the first speed, and wherein the first differential amplifier is configured to reduce or increase the signals sent and received at the first speed or the signals sent and received at the second speed.