US 12,066,475 B2
Two-step charge-based capacitor measurement
Tai-Yi Chen, Hsinchu (TW); Chung-Chieh Yang, Hsinchu (TW); Chih-Chiang Chang, Taipei (TW); and Chung-Ting Lu, Kaohsiung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 15, 2021, as Appl. No. 17/231,312.
Claims priority of provisional application 63/031,830, filed on May 29, 2020.
Prior Publication US 2021/0373059 A1, Dec. 2, 2021
Int. Cl. G01R 27/26 (2006.01); G01R 31/26 (2020.01); G01R 31/28 (2006.01); H03K 19/094 (2006.01)
CPC G01R 27/2605 (2013.01) [G01R 31/2639 (2013.01); G01R 31/2841 (2013.01); H03K 19/094 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method comprising:
applying a first voltage to a first transistor of a first pseudo-inverter circuit and a second voltage to a second transistor of a second pseudo-inverter circuit, wherein a device under test is coupled between the first pseudo-inverter circuit and the second pseudo-inverter circuit, a third transistor is coupled between the first transistor and ground, and a fourth transistor is coupled between the second transistor and the ground; and
performing only two measurement steps, wherein:
during a first measurement step, the first and fourth transistors are turned on, the second and third transistors are turned off, and a first current, induced by a capacitance of the device under test and a parasitic capacitance, is measured; and
during a second measurement step, the first and second transistors are turned on, the third and fourth transistors are turned off, and a second current, induced by the parasitic capacitance, is measured, and wherein a capacitance (Cdut) of the device under test is expressed as follows:

OG Complex Work Unit Math
where Iac1 is the first current, Iac2 is the second current, Vdd1 is the first voltage, and f is a clock frequency.