US 11,737,325 B2
Display panel comprising a data line including electrically-connected sub-data lines and display device having the same
Xingxing Yang, Wuhan (CN); Yangzhao Ma, Wuhan (CN); and Zhiqiang Xia, Wuhan (CN)
Assigned to WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., Wuhan (CN)
Filed by Wuhan Tianma Micro-Electronics Co., Ltd., Wuhan (CN)
Filed on Mar. 5, 2021, as Appl. No. 17/193,146.
Claims priority of application No. 202010875868.1 (CN), filed on Aug. 27, 2020.
Prior Publication US 2022/0069047 A1, Mar. 3, 2022
Int. Cl. H01L 29/12 (2006.01); H10K 59/131 (2023.01); H10K 59/88 (2023.01); H10K 59/121 (2023.01); H01L 27/12 (2006.01); H10K 59/35 (2023.01)
CPC H10K 59/131 (2023.02) [H10K 59/1213 (2023.02); H10K 59/1216 (2023.02); H10K 59/88 (2023.02); H01L 27/1214 (2013.01); H10K 59/35 (2023.02)] 29 Claims
OG exemplary drawing
 
1. A display panel, comprising:
a first display region, a second display region, and a third display region, wherein the second display region at least partially surrounds the first display region, the third display region at least partially surrounds the second display region and the first display region, a light transmittance of the first display region is greater than a light transmittance of the third display region, and the first display region includes an effective light-transmission region and a wiring region located on at least one side of the effective light-transmission region;
a plurality of first pixel circuits, a plurality of second pixel circuits, and a plurality of third pixel circuits, wherein the plurality of first pixel circuits and the plurality of second pixel circuits are located in the second display region, and the plurality of third pixel circuits are located in the third display region;
a plurality of first data lines, connected to the plurality of first pixel circuits and the plurality of third pixel circuits, wherein each first data line includes a first sub-data line, a second sub-data line, and a third sub-data line that are electrically connected together, the wiring region is provided with a plurality of first sub-data lines, the second display region is provided with a plurality of second sub-data lines, and the third display region is provided with a plurality of third sub-data lines; and
a plurality of second data lines, connected to the plurality of second pixel circuits and the plurality of third pixel circuits.