CPC H10B 63/30 (2023.02) [H10B 53/30 (2023.02); H10B 61/22 (2023.02)] | 20 Claims |
20. A memory device comprising:
a substrate;
a bit line disposed on the substrate;
a memory cell disposed on the bit line;
a first dielectric layer disposed on the substrate, surrounding the bit line and the memory cell;
a second dielectric layer disposed on the first dielectric layer;
a thin film transistor (TFT) embedded in the second dielectric layer and configured to selectively provide electric power to the memory cell; and
a word line disposed on the second dielectric layer and electrically connected to the TFT.
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