US 11,737,283 B1
Method of forming a stack of non-planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell
Rajeev Kumar Dokania, Beaverton, OR (US); Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Amrita Mathuriya, Portland, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Nov. 1, 2021, as Appl. No. 17/516,594.
Application 17/516,594 is a continuation of application No. 17/516,293, filed on Nov. 1, 2021.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); H10B 53/30 (2023.01); G11C 11/24 (2006.01)
CPC H10B 53/30 (2023.02) [G11C 11/24 (2013.01)] 20 Claims
OG exemplary drawing
 
20. A method comprising:
forming a memory;
storing one or more instructions on the memory;
executing, by a processor circuitry, the one or more instructions; and
allowing, via a communication interface, the processor circuitry to communicate with another device, wherein forming the memory includes:
forming a via extending along a y-plane, wherein the y-plane is orthogonal to an x-plane, and wherein the via couples to a first metal layer;
forming a first capacitor including a non-linear polar material, wherein the first capacitor includes an electrode coupled to the via, and wherein the electrode is in a middle of the first capacitor;
forming a second capacitor including a linear dielectric material, wherein the electrode passes through a middle of the second capacitor;
forming a first plate-line extending along the x-plane or a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane, and wherein the first plate-line is on first outer portion of the first capacitor; and
forming a second plate-line extending along the x-plane or the z-plane, wherein the second plate-line is on second output portion of the second capacitor, and wherein the second plate-line has a second voltage complementary to a first voltage on the first plate-line.