CPC H10B 53/30 (2023.02) [G11C 11/24 (2013.01)] | 20 Claims |
20. A method comprising:
forming a memory;
storing one or more instructions on the memory;
executing, by a processor circuitry, the one or more instructions; and
allowing, via a communication interface, the processor circuitry to communicate with another device, wherein forming the memory includes:
forming a via extending along a y-plane, wherein the y-plane is orthogonal to an x-plane, and wherein the via couples to a first metal layer;
forming a first capacitor including a non-linear polar material, wherein the first capacitor includes an electrode coupled to the via, and wherein the electrode is in a middle of the first capacitor;
forming a second capacitor including a linear dielectric material, wherein the electrode passes through a middle of the second capacitor;
forming a first plate-line extending along the x-plane or a z-plane, wherein the z-plane is orthogonal to the x-plane and the y-plane, and wherein the first plate-line is on first outer portion of the first capacitor; and
forming a second plate-line extending along the x-plane or the z-plane, wherein the second plate-line is on second output portion of the second capacitor, and wherein the second plate-line has a second voltage complementary to a first voltage on the first plate-line.
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