US 11,737,227 B2
Selective ground flood around reduced land pad on package base layer to enable high speed land grid array (LGA) socket
Zhichao Zhang, Chandler, AZ (US); Gregorio R. Murtagian, Phoenix, AZ (US); Kuang C. Liu, Queen Creek, AZ (US); and Kemal Aygun, Tempe, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 22, 2022, as Appl. No. 17/677,785.
Application 17/677,785 is a continuation of application No. 15/938,980, filed on Mar. 28, 2018, granted, now 11,291,133.
Prior Publication US 2022/0183177 A1, Jun. 9, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H05K 7/10 (2006.01); H05K 1/11 (2006.01); H05K 1/02 (2006.01); H01R 13/24 (2006.01)
CPC H05K 7/1061 (2013.01) [H01R 13/24 (2013.01); H05K 1/0253 (2013.01); H05K 1/112 (2013.01); H05K 2201/093 (2013.01); H05K 2201/09609 (2013.01); H05K 2201/10719 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A socket assembly, comprising:
a socket having an interconnect in a housing body, the interconnect includes a vertical portion and a horizontal portion, wherein the housing body has a top surface and a bottom surface that is opposite from the top surface, wherein the top surface is a conductive layer; and
a package having a base layer, the base layer includes a signal pad and a ground strip, wherein the base layer is above the conductive layer of the housing body of the socket, wherein the ground strip is vertically over the horizontal portion of the interconnect of the socket, and wherein the horizontal portion is coupled to the signal pad on the base layer.