CPC H04N 19/174 (2014.11) [H04N 19/436 (2014.11)] | 18 Claims |
1. An apparatus comprising:
a video hardware accelerator unit; and
a controller coupled to the video hardware accelerator unit, the controller configured to process a plurality of frames with a plurality of threads,
wherein the plurality of threads includes:
a communication thread configured to communicate with a processing unit;
a kernel thread configured to schedule the plurality of frames;
a frame thread configured to process encode attributes associated with the plurality of frames and to generate encode parameters associated with the plurality of frames;
a hardware thread configured to configure the video hardware accelerator unit to process the plurality of frames based on the encode parameters; and
a slice thread configured to process slices associated with the plurality of frames.
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