US 11,736,402 B2
Fast data center congestion response based on QoS of VL
Vignesh Trichy Ravi, Portland, OR (US); Ravi Murty, Portland, OR (US); Ravindra Babu Ganapathi, Hillsboro, OR (US); and Michael A. Parker, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 13, 2021, as Appl. No. 17/499,949.
Application 17/499,949 is a continuation of application No. 15/836,850, filed on Dec. 9, 2017, granted, now 11,153,211.
Prior Publication US 2022/0141138 A1, May 5, 2022
Int. Cl. H04L 1/00 (2006.01); H04L 47/12 (2022.01); H04L 47/11 (2022.01); H04L 47/30 (2022.01); H04L 47/2425 (2022.01); H04L 47/2483 (2022.01); H04L 47/263 (2022.01)
CPC H04L 47/12 (2013.01) [H04L 47/11 (2013.01); H04L 47/2425 (2013.01); H04L 47/2483 (2013.01); H04L 47/263 (2013.01); H04L 47/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic circuit, comprising circuitry to:
provide switching of network traffic between an ingress port and a plurality of egress ports, including assigning packets to one of a plurality of virtual lanes (VLs);
receive a quality of service (QoS) metric for a VL;
determine that congestion inhibits the VL from meeting the QoS metric;
calculate a quantitative flow throttle value for the VL; and
based on the determining, send a link layer congestion control message to a source host of packets for the VL, wherein the congestion control message is to realize the quantitative flow throttle value for the VL.