US 11,736,269 B2
Low-complexity synchronization header detection
Wenxun Qiu, Allen, TX (US); Tomas Motos, Hamar (NO); and Marius Moe, Fetsund (NO)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Sep. 29, 2021, as Appl. No. 17/488,364.
Application 17/488,364 is a continuation of application No. 17/028,328, filed on Sep. 22, 2020.
Application 17/028,328 is a continuation of application No. 16/210,420, filed on Dec. 5, 2018, abandoned.
Prior Publication US 2022/0021514 A1, Jan. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 7/04 (2006.01); H04L 27/34 (2006.01); H04L 27/38 (2006.01); H04B 1/7073 (2011.01)
CPC H04L 7/042 (2013.01) [H04B 1/70735 (2013.01); H04L 27/3405 (2013.01); H04L 27/3455 (2013.01); H04L 27/3836 (2013.01); H04B 2201/7073 (2013.01); H04L 2212/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A start field delimiter detector, comprising:
a minimum-shift keying (MSK) demodulation circuit, configured to translate offset quadrature phase shift keying chips into a set of sequences of MSK symbols;
a first circuit, configured to compare whether a first portion of each sequence of MSK symbols matches with a first portion of a respective sequence of reference MSK symbols;
a second circuit, configured to compare whether a second portion of each sequence of MSK symbols matches with a second portion of the respective sequence of reference MSK symbols, wherein the second portion of each respective sequence of reference MSK symbols is invariant; and
a start field delimiter detector circuit configured to indicate detection of a start field delimiter in a packet responsive to the comparison by the first circuit and the comparison by the second circuit.