US 11,735,671 B2
Method and system for fabrication of a vertical fin-based field effect transistor
Clifford Drowley, Santa Clara, CA (US); Ray Milano, Santa Clara, CA (US); Subhash Srinivas Pidaparthi, Santa Clara, CA (US); Andrew P. Edwards, Santa Clara, CA (US); Hao Cui, Santa Clara, CA (US); and Shahin Sharifzadeh, Santa Clara, CA (US)
Assigned to Nexgen Power Systems, Inc., Santa Clara, CA (US)
Filed by NEXGEN POWER SYSTEMS, INC., Santa Clara, CA (US)
Filed on Apr. 12, 2022, as Appl. No. 17/719,221.
Application 17/719,221 is a division of application No. 16/929,926, filed on Jul. 15, 2020, granted, now 11,335,810.
Claims priority of provisional application 62/877,224, filed on Jul. 22, 2019.
Prior Publication US 2022/0310843 A1, Sep. 29, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 29/778 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7856 (2013.01) [H01L 29/6653 (2013.01); H01L 29/66803 (2013.01); H01L 29/7783 (2013.01); H01L 29/7788 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A method of fabricating a vertical fin-based field effect transistor (FET), the method comprising:
providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type;
epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer;
epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer;
forming a metal compound layer on the second semiconductor layer;
forming a patterned hard mask layer on the metal compound layer;
etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench; and
terminating the etching in the graded doping layer.