US 11,735,658 B2
Tunnel field-effect transistor with reduced subthreshold swing
Xin Miao, Slingerlands, NY (US); Chen Zhang, Guilderland, NY (US); Kangguo Cheng, Schenectady, NY (US); and Wenyu Xu, Albany, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jan. 15, 2020, as Appl. No. 16/743,637.
Application 16/743,637 is a division of application No. 15/996,638, filed on Jun. 4, 2018, granted, now 10,644,150.
Prior Publication US 2020/0152790 A1, May 14, 2020
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/207 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7827 (2013.01) [H01L 21/0262 (2013.01); H01L 21/02546 (2013.01); H01L 21/30621 (2013.01); H01L 29/0657 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H01L 29/207 (2013.01); H01L 29/66522 (2013.01); H01L 29/66666 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
at least one fin on a semiconductor substrate, the at least one fin comprising a channel layer stacked on top of a source layer and a drain layer stacked on top of the channel layer;
a cap layer disposed on a lower portion of the at least one fin comprising the source layer and part of the channel layer; and
a gate structure comprising a gate dielectric layer and a gate conductor disposed on the at least one fin and on the cap layer;
wherein the cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer; and
wherein the cap layer extends perpendicularly with respect to a top surface of the semiconductor substrate along a lateral side of the at least one fin to an uppermost height below the top of the channel layer;
wherein a first portion of the gate dielectric layer is disposed on a side of the cap layer, and a second portion of the gate dielectric layer is disposed on a part of the lateral side of the at least one fin without the cap layer positioned between the part of the lateral side of the at least one fin and the second portion of the gate dielectric layer; and
wherein the lattice constants of the cap layer, of the channel layer and of the source layer are the same.