US 11,735,652 B2
Field effect transistors having ferroelectric or antiferroelectric gate dielectric structure
Seiyon Kim, Portland, OR (US); Uygar E. Avci, Portland, OR (US); Joshua M. Howard, Portland, OR (US); Ian A. Young, Portland, OR (US); and Daniel H. Morris, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Appl. No. 16/635,739
Filed by Intel Corporation, Santa Clara, CA (US)
PCT Filed Sep. 28, 2017, PCT No. PCT/US2017/054164
§ 371(c)(1), (2) Date Jan. 31, 2020,
PCT Pub. No. WO2019/066875, PCT Pub. Date Apr. 4, 2019.
Prior Publication US 2020/0321446 A1, Oct. 8, 2020
Int. Cl. H01L 29/66 (2006.01); H01L 29/51 (2006.01)
CPC H01L 29/6684 (2013.01) [H01L 29/516 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a semiconductor channel structure comprising a monocrystalline material;
a gate dielectric over the semiconductor channel structure, the gate dielectric comprising a ferroelectric or antiferroelectric polycrystalline material layer, the ferroelectric or antiferroelectric polycrystalline material layer having an uppermost surface, and the gate dielectric further comprising an amorphous oxide layer between the ferroelectric or antiferroelectric polycrystalline material layer and the semiconductor channel structure, wherein the ferroelectric or antiferroelectric polycrystalline material layer is on and in direct contact with the amorphous oxide layer, and wherein the amorphous oxide layer is on and in direct contact with the semiconductor channel structure;
a gate electrode having a conductive layer on and in direct contact with the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer comprising a metal, and the conductive layer having an uppermost surface co-planar with the uppermost surface of the ferroelectric or antiferroelectric polycrystalline material layer, and the gate electrode having a gate fill layer on and in direct contact with the conductive layer;
a first source or drain structure at a first side of the gate electrode; and
a second source or drain structure at a second side of the gate electrode opposite the first side.