US 11,735,599 B2
Semiconductor device and semiconductor device identification method
Naoki Matsumoto, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Appl. No. 16/971,556
Filed by ROHM CO., LTD., Kyoto (JP)
PCT Filed Mar. 8, 2019, PCT No. PCT/JP2019/009343
§ 371(c)(1), (2) Date Aug. 20, 2020,
PCT Pub. No. WO2019/176774, PCT Pub. Date Sep. 19, 2019.
Claims priority of application No. 2018-044398 (JP), filed on Mar. 12, 2018.
Prior Publication US 2021/0091119 A1, Mar. 25, 2021
Int. Cl. H01L 27/12 (2006.01); G01R 31/28 (2006.01); H01L 21/822 (2006.01)
CPC H01L 27/124 (2013.01) [G01R 31/28 (2013.01); H01L 21/822 (2013.01); H01L 27/1225 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first external terminal to which a first voltage is to be applied;
a second external terminal to which a second voltage is to be applied;
a third external terminal;
first wiring connected to the first external terminal;
second wiring connected to the second external terminal;
a first internal block circuit connected to the first wiring;
a first resistor and a first switching element serially connected between the first wiring and the second wiring;
a second resistor connected between the first wiring and the second wiring; and
a test circuit that is connected to the third external terminal, that turns on and off the first switching element based on a signal from the third external terminal,
wherein a resistance value of the second resistor is larger than a resistance value of the first resistor.