US 11,735,549 B2
Methods and systems for manufacturing pillar structures on semiconductor devices
Suresh Yeruva, Boise, ID (US); Owen R. Fay, Meridian, ID (US); Sameer S. Vadhavkar, Boise, ID (US); Adriel Jebin Jacob Jebaraj, Boise, ID (US); and Wayne H. Huang, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 15, 2021, as Appl. No. 17/376,934.
Application 17/376,934 is a division of application No. 16/236,237, filed on Dec. 28, 2018, granted, now 11,081,460.
Prior Publication US 2021/0343670 A1, Nov. 4, 2021
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/14 (2013.01) [H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/1146 (2013.01); H01L 2224/11614 (2013.01); H01L 2224/13083 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/14517 (2013.01); H01L 2924/35121 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a conductive substrate having a first surface and a second surface opposite the first surface;
passivation material covering a portion of the first surface of the conductive substrate;
a first pillar comprising a base layer in contact with the passivation material and a second layer plated to the base layer opposite the passivation material;
a second pillar comprising a base layer in contact with the first surface of the conductive substrate and a second layer in contact with the base layer of the second pillar opposite the first surface of the conductive substrate;
wherein:
the base layer of the first pillar has a first width;
the second layer of the first pillar has a second width greater than the first width;
the base layer of the second pillar has a third width;
the second layer of the second pillar has a fourth width.