US 11,735,533 B2
Heterogeneous nested interposer package for IC chips
Debendra Mallik, Chandler, AZ (US); Ravindranath Mahajan, Chandler, AZ (US); Robert Sankman, Phoenix, AZ (US); Shawna Liff, Scottsdale, AZ (US); Srinivas Pietambaram, Chandler, AZ (US); and Bharat Penmecha, Phoenix, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 11, 2019, as Appl. No. 16/437,254.
Prior Publication US 2020/0395313 A1, Dec. 17, 2020
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/5381 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/3511 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An electronic package, comprising:
an interposer, wherein a cavity passes through the interposer;
a nested component in the cavity; and
a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect, wherein the first and second interconnects comprise:
a first bump;
a bump pad over the first bump; and
a second bump over the bump pad.