US 11,735,516 B2
Metal-oxide-metal (MOM) capacitors for integrated circuit monitoring
Yaojian Leng, Vancouver, WA (US); and Justin Sato, West Linn, OR (US)
Assigned to Microchip Technology Incorporated, Chandler, AZ (US)
Filed by Microchip Technology Incorporated, Chandler, AZ (US)
Filed on May 3, 2021, as Appl. No. 17/306,019.
Claims priority of provisional application 63/105,169, filed on Oct. 23, 2020.
Prior Publication US 2022/0130753 A1, Apr. 28, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 21/66 (2006.01); H01L 23/528 (2006.01); H01L 49/02 (2006.01); H01L 21/67 (2006.01)
CPC H01L 23/5223 (2013.01) [H01L 21/67259 (2013.01); H01L 22/20 (2013.01); H01L 22/34 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 28/40 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method of evaluating an integrated circuit structure, the method comprising:
forming a plurality of metal-oxide-metal (MOM) capacitors in a plurality of patterned layers of the integrated circuit structure;
wherein each of the plurality of MOM capacitors is formed with a different alignment between the patterned layers in at least one direction;
performing electrical testing of the plurality of MOM capacitors; and
determining a patterned layer misalignment in the plurality of patterned layers based on the electrical testing.