CPC H01L 23/5223 (2013.01) [H01L 21/67259 (2013.01); H01L 22/20 (2013.01); H01L 22/34 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 28/40 (2013.01)] | 14 Claims |
1. A method of evaluating an integrated circuit structure, the method comprising:
forming a plurality of metal-oxide-metal (MOM) capacitors in a plurality of patterned layers of the integrated circuit structure;
wherein each of the plurality of MOM capacitors is formed with a different alignment between the patterned layers in at least one direction;
performing electrical testing of the plurality of MOM capacitors; and
determining a patterned layer misalignment in the plurality of patterned layers based on the electrical testing.
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