CPC G11C 16/30 (2013.01) [G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 16/3404 (2013.01)] | 25 Claims |
1. A method, comprising:
receiving, at a memory device, a command to write information to memory cells comprising a chalcogenide material and configured to store a set state, a reset state, and an intermediate state; and
writing a memory cell of the memory device to the intermediate state based at least in part on receiving the command, wherein writing the memory cell to the intermediate state comprises:
applying a first pulse having a first polarity to the memory cell, the first pulse configured to condition the memory cell;
isolating a first access line coupled with the memory cell from a voltage source based at least in part on applying the first pulse having the first polarity; and
applying a second pulse to a second access line coupled with the memory cell based at least in part on isolating the first access line coupled with the memory cell.
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