US 11,735,272 B2
Noise reduction during parallel plane access in a multi-plane memory device
Theodore Pekny, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 10, 2022, as Appl. No. 17/572,057.
Application 17/572,057 is a continuation of application No. 16/946,867, filed on Jul. 9, 2020, granted, now 11,222,702.
Prior Publication US 2022/0199169 A1, Jun. 23, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/26 (2006.01); G06F 12/0802 (2016.01); G11C 16/04 (2006.01)
CPC G11C 16/26 (2013.01) [G06F 12/0802 (2013.01); G11C 16/04 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory array comprising a plurality of planes;
a plurality of independent plane driver circuits operatively coupled with the plurality of planes; and
control logic, operatively coupled with the plurality of independent plane driver circuits, to perform operations comprising:
detecting an occurrence of a high noise event associated with a first independent plane driver circuit of the plurality of independent plane driver circuits, the first independent plane driver circuit corresponding to a first plane of the plurality of planes;
determining whether a quiet event associated with a second independent plane driver circuit of the plurality of independent plane driver circuits is concurrently occurring, the second independent plane driver circuit corresponding to a second plane of the plurality of planes; and
responsive to determining that the quiet event associated with the second independent plane driver circuit is concurrently occurring, managing execution of the high noise event and the quiet event based on respective priorities of the first and second independent plane driver circuits.