CPC G11C 16/16 (2013.01) [G11C 11/5635 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/3445 (2013.01); G11C 11/5671 (2013.01); G11C 16/3409 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] | 20 Claims |
1. A memory device comprising:
a memory array of NAND memory cells; and
a memory controller configured to perform operations comprising:
rendering a value stored in a first page of the memory array unreadable by applying a pre-programming pulse to memory cells of the first page without applying an erase pulse until a later garbage collection operation, the pre-programming pulse changing a voltage level of each of the respective memory cells of the first page to a same level.
|