US 11,735,268 B2
Memory devices for suspend and resume operations
Umberto Siciliani, Rubano (IT); Floriano Montemurro, Albignasego (IT); Eric N. Lee, San Jose, CA (US); and Dheeraj Srinivasan, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Jul. 22, 2021, as Appl. No. 17/382,619.
Claims priority of provisional application 63/131,830, filed on Dec. 30, 2020.
Prior Publication US 2022/0208273 A1, Jun. 30, 2022
Int. Cl. G11C 16/14 (2006.01); G11C 16/10 (2006.01); G11C 7/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/14 (2013.01) [G11C 7/106 (2013.01); G11C 7/1063 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A memory device comprising:
an array of memory cells; and
a controller configured to access the array of memory cells,
wherein the controller is further configured to:
receive a command to perform an erase operation;
in response to the command to perform the erase operation, begin execution of the erase operation;
in response to executing the erase operation, pull down a ready/busy control signal to indicate the memory device is busy executing the erase operation;
while executing the erase operation, receive a command to perform a program operation with the ready/busy control signal pulled down;
in response to the command to perform the program operation, suspend the execution of the erase operation while keeping the ready/busy control signal pulled down; and
with the execution of the erase operation suspended, execute the program operation while keeping the ready/busy control signal pulled down.