CPC G11C 16/14 (2013.01) [G11C 7/106 (2013.01); G11C 7/1063 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01)] | 22 Claims |
1. A memory device comprising:
an array of memory cells; and
a controller configured to access the array of memory cells,
wherein the controller is further configured to:
receive a command to perform an erase operation;
in response to the command to perform the erase operation, begin execution of the erase operation;
in response to executing the erase operation, pull down a ready/busy control signal to indicate the memory device is busy executing the erase operation;
while executing the erase operation, receive a command to perform a program operation with the ready/busy control signal pulled down;
in response to the command to perform the program operation, suspend the execution of the erase operation while keeping the ready/busy control signal pulled down; and
with the execution of the erase operation suspended, execute the program operation while keeping the ready/busy control signal pulled down.
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