US 11,735,254 B2
Error avoidance based on voltage distribution parameters of blocks
Shane Nowell, Boise, ID (US); Steven Michael Kientz, Westminster, CO (US); Michael Sheperek, Longmont, CO (US); Mustafa N Kaynak, San Diego, CA (US); Kishore Kumar Muchherla, San Jose, CA (US); Larry J Koudele, Erie, CO (US); and Bruce A Liikanen, Berthoud, CO (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Mar. 30, 2021, as Appl. No. 17/217,772.
Prior Publication US 2022/0319589 A1, Oct. 6, 2022
Int. Cl. G11C 11/34 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01)
CPC G11C 11/5642 (2013.01) [G11C 11/5628 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, by a processing device, a request to read data from a block of a memory device coupled with the processing device;
determining, using a data structure which maps block identifiers to voltage distribution parameter values, a voltage distribution parameter value for the block of the memory device;
responsive to determining that a block identifier value for the block is not mapped to any voltage distribution parameter values, determining a corresponding voltage distribution parameter value for the block based on a voltage distribution of one or more memory cells comprised by the block of the memory device;
determining, for the block of the memory device, a set of read levels based on the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of the memory cells comprised by the block of the memory device; and
reading, using the set of read levels based on the voltage distribution parameter value, data from the block of the memory device.