| CPC G11C 11/4091 (2013.01) [G11C 5/063 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4096 (2013.01)] | 25 Claims |
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1. A method, comprising:
selecting, for a read operation, a pair of memory cells that comprises a first memory cell coupled with a first digit line and a second memory cell coupled with a second digit line, the pair of memory cells configured to store a single bit of information;
applying a first voltage to a plate line coupled with the first memory cell and the second memory cell of the pair of memory cells;
applying a second voltage to a select line to couple the first digit line and the second digit line with a sense amplifier based at least in part on applying the first voltage to the plate line;
sensing, after applying the second voltage, a logic state stored by the pair of memory cells based at least in part on a difference between a third voltage of the first digit line and a fourth voltage of the second digit line;
applying, simultaneously with sensing the logic state, a fifth voltage to a first capacitor coupled with the first digit line and the sense amplifier to pull down the first digit line from a sixth voltage to the third voltage based at least in part on coupling the first digit line to the sense amplifier; and
applying, simultaneously with sensing the logic state, a seventh voltage to a second capacitor coupled with the second digit line and the sense amplifier to pull down the second digit line from an eighth voltage to the fourth voltage based at least in part on coupling the second digit line to the sense amplifier.
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