US 11,735,246 B2
Semiconductor device performing refresh operation
Atsushi Hatakeyama, Kokubunji (JP); Hyun Yoo Lee, Boise, ID (US); Kang-Yong Kim, Boise, ID (US); and Akiyoshi Yamamoto, Sagamihara (JP)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Nov. 15, 2021, as Appl. No. 17/454,963.
Prior Publication US 2023/0154520 A1, May 18, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 11/406 (2006.01)
CPC G11C 11/40618 (2013.01) [G11C 11/40615 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of memory banks; and
a refresh controller configured to perform a refresh operation on one or more of the plurality of memory banks having a first state without performing the refresh operation on one or more of the plurality of memory banks having a second state responsive to a first refresh command, and perform the refresh operation on a selected one of the plurality of memory banks responsive to a second refresh command,
wherein the refresh controller is configured to bring the selected one of the plurality of memory banks into the second state when the refresh operation is performed responsive to the second refresh command.