US 11,735,245 B1
Read scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize read or write disturb effects
Rajeev Kumar Dokania, Beaverton, OR (US); Amrita Mathuriya, Portland, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Nov. 22, 2021, as Appl. No. 17/532,552.
Application 17/532,552 is a continuation of application No. 17/529,258, filed on Nov. 17, 2021, granted, now 11,482,270.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); G11C 11/22 (2006.01)
CPC G11C 11/2275 (2013.01) [G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/2273 (2013.01); G11C 11/2297 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first node;
a second node;
a first capacitor comprising non-linear polar material, the first capacitor having a first terminal coupled to the first node and a second terminal coupled to a first plate-line;
a second capacitor comprising the non-linear polar material, the second capacitor having a third terminal coupled to the first node and a fourth terminal coupled to a second plate-line;
a first transistor coupled to the first node and a bit-line, wherein the first transistor is controllable by a word-line, wherein the first plate-line and the second plate-line are parallel to the word-line;
a second transistor having a gate terminal coupled to the first node, and a source terminal coupled to a sense-line and a drain terminal coupled to the second node; and
one or more circuitries to boost the word-line during a read operation.