US 11,735,234 B2
Differential amplifier schemes for sensing memory cells
Daniele Vimercati, El Dorado Hills, CA (US); and Xinwei Guo, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 21, 2021, as Appl. No. 17/557,825.
Application 17/557,825 is a continuation of application No. 16/702,422, filed on Dec. 3, 2019, granted, now 11,211,101.
Prior Publication US 2022/0189514 A1, Jun. 16, 2022
Int. Cl. G11C 27/02 (2006.01); G11C 7/06 (2006.01); H03F 3/45 (2006.01); G11C 11/16 (2006.01); G11C 11/15 (2006.01)
CPC G11C 7/062 (2013.01) [G11C 11/15 (2013.01); G11C 11/1657 (2013.01); H03F 3/45076 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a capacitive element having a first node and a second node, wherein the capacitive element is configured to store an absolute value of charge that increases non-linearly as an absolute voltage between the first node and the second node increases;
a first transistor, wherein a gate of the first transistor and a source of the first transistor are connected to the first node and wherein a drain of the first transistor is connected to the second node; and
a second transistor, wherein a gate of the second transistor and a source of the second transistor are connected to the second node and wherein a drain of the second transistor is connected to the first node.