US 11,735,120 B2
Scanning-line driving circuit and display device provided with same
Masahiro Mitani, Sakai (JP); Makoto Yokoyama, Sakai (JP); and Naoki Ueda, Sakai (JP)
Assigned to SHARP KABUSHIKI KAISHA, Sakai (JP)
Appl. No. 17/908,003
Filed by Sharp Kabushiki Kaisha, Sakai (JP)
PCT Filed Mar. 2, 2020, PCT No. PCT/JP2020/008640
§ 371(c)(1), (2) Date Aug. 30, 2022,
PCT Pub. No. WO2021/176504, PCT Pub. Date Sep. 10, 2021.
Prior Publication US 2023/0112313 A1, Apr. 13, 2023
Int. Cl. G09G 3/3266 (2016.01); G09G 3/325 (2016.01); G09G 3/3291 (2016.01)
CPC G09G 3/3266 (2013.01) [G09G 3/325 (2013.01); G09G 3/3291 (2013.01); G09G 2300/0426 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A scanning-line driving circuit configured with a plurality of unit circuits cascaded in stages and integrally formed with a display panel, wherein,
the unit circuit includes:
a first transistor that has a first conductive electrode supplied with a first-level voltage and a second conductive electrode connected to a first node;
a resistor connected to the first node at a first terminal;
a second transistor that has a first conductive electrode supplied with a second-level voltage and a second conductive electrode connected to a second terminal of the resistor; and
an output transistor that has a control electrode connected to the first node and a first conductive electrode connected to an output terminal,
the resistor is formed in the same semiconductor layer as semiconductor portions of the first and second transistors, and
the unit circuit further includes an upper electrode formed above the resistor.