US 11,734,597 B2
Frequency allocation in multi-qubit circuits
Jared Barney Hertzberg, Westchester, NY (US); Sami Rosenblatt, White Plains, NY (US); Easwar Magesan, Mount Kisco, NY (US); and John Aaron Smolin, Yorktown, NY (US)
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Apr. 26, 2021, as Appl. No. 17/240,095.
Application 17/240,095 is a division of application No. 16/552,365, filed on Aug. 27, 2019, granted, now 11,010,685.
Application 16/552,365 is a continuation of application No. 16/002,817, filed on Jun. 7, 2018, granted, now 10,423,888, issued on Sep. 24, 2019.
Prior Publication US 2021/0241161 A1, Aug. 5, 2021
Int. Cl. G06N 10/00 (2022.01); H10N 99/00 (2023.01); G06F 13/40 (2006.01); B82Y 10/00 (2011.01)
CPC G06N 10/00 (2019.01) [G06F 13/4068 (2013.01); H10N 99/05 (2023.02); B82Y 10/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory that stores computer executable components; and
a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise:
a performance analysis component that analyzes simulated performance of respective qubit chip features and determines operation metrics for the respective qubit chip features at respective frequency offsets; and
a design generation component that generates a superconducting qubit chip design using one or more of the respective qubit chip features based on the respective operation metrics determined by the performance analysis component.