US 11,734,484 B2
Method for automating semiconductor design based on artificial intelligence
Jinwoo Park, Gyeonggi-do (KR); Wooshik Myung, Seoul (KR); Kyeongmin Woo, Seoul (KR); and Jiyoon Lim, Seoul (KR)
Assigned to MAKINAROCKS CO., LTD., Seoul (KR)
Filed by MakinaRocks Co., Ltd., Seoul (KR)
Filed on Nov. 14, 2022, as Appl. No. 17/986,167.
Claims priority of application No. 10-2021-0159381 (KR), filed on Nov. 18, 2021; and application No. 10-2022-0083785 (KR), filed on Jul. 7, 2022.
Prior Publication US 2023/0153506 A1, May 18, 2023
Int. Cl. G06F 30/392 (2020.01); G06F 30/31 (2020.01); G06N 3/045 (2023.01); G06F 30/327 (2020.01); G06F 30/394 (2020.01)
CPC G06F 30/392 (2020.01) [G06F 30/31 (2020.01); G06F 30/327 (2020.01); G06F 30/394 (2020.01); G06N 3/045 (2023.01)] 14 Claims
OG exemplary drawing
 
1. A method for automating a semiconductor design based on artificial intelligence, the method performed by a computing device including at least one processor, the method comprising:
generating a first mask to be placed in a canvas;
generating a first embedding for a semiconductor element to be placed in the canvas in an area where the first mask is not placed and based on feature information and logical design information of the semiconductor element by using a first neural network; and
generating a probability distribution for placing the semiconductor element based on the first embedding and a second embedding for semiconductor elements already placed in the canvas by using a second neural network,
wherein the first neural network and the second neural network are pre-trained through a reward,
wherein the reward is computed by a weighted sum of a length of a wire connecting the semiconductor elements placed in the canvas, and a congestion of the semiconductor elements placed in the canvas, and
wherein the congestion of the semiconductor elements are maximally evenly distributed.