US 11,734,480 B2
Performance modeling and analysis of microprocessors using dependency graphs
Gagan Gupta, Bellevue, WA (US); Rathijit Sen, Madison, WI (US); and Hossein Golestani, Ann Arbor, MI (US)
Assigned to MICROSOFT TECHNOLOGY LICENSING, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Dec. 18, 2018, as Appl. No. 16/224,718.
Prior Publication US 2020/0192994 A1, Jun. 18, 2020
Int. Cl. G06F 30/30 (2020.01); G06F 11/34 (2006.01)
CPC G06F 30/30 (2020.01) [G06F 11/3447 (2013.01); G06F 11/3466 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method performed by a computer-implemented microarchitecture modeling tool, comprising:
receiving an execution trace generated based on an execution of a program, a definition of a microarchitecture on which the program was executed, and a policy that specifies how the microarchitecture handles a structural hazard;
generating a dependency graph based at least on the execution trace, the definition and the policy, the dependency graph being a representation of the execution of the program, wherein generating the dependency graph comprises:
generating a plurality of vertices, each vertex of the plurality of vertices specifying a particular microarchitectural event that occurred during execution of the program,
generating a plurality of edges, each edge of the plurality of edges coupling a vertex of the plurality of vertices to at least another vertex of the plurality of vertices and representing a dependency between the microarchitectural events specified by edge-coupled vertices, and
generating at least one edge connecting a plurality of vertices associated with a structural hazard;
associating at least one of each vertex of the plurality of vertices with a microarchitectural event cost for performing a first microarchitectural event specified thereby or each edge of the plurality of edges with a second microarchitectural event specified by at least one vertex of the plurality of vertices coupled thereto;
determining a first design metric of the microarchitecture based on an analysis of the microarchitectural event costs associated with at least one of the plurality of vertices or the plurality of edges;
and
implementing a change modeled in the microarchitecture via the dependency graph in a hardware-based architecture.