US 11,734,203 B2
Response-based interconnect control
Robert Walker, Raleigh, NC (US); and Nikesh Agarwal, Bangalore (IN)
Assigned to Micron Technologies, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 20, 2021, as Appl. No. 17/556,908.
Prior Publication US 2023/0195656 A1, Jun. 22, 2023
Int. Cl. G06F 13/16 (2006.01); H04L 47/10 (2022.01); G06F 9/30 (2018.01)
CPC G06F 13/1621 (2013.01) [G06F 9/30043 (2013.01); G06F 9/30101 (2013.01); G06F 13/1642 (2013.01); G06F 13/1668 (2013.01); H04L 47/39 (2013.01)] 45 Claims
OG exemplary drawing
 
1. A method comprising:
storing multiple memory responses in a response queue at a memory device;
tracking, by the memory device, a quantity of the multiple memory responses stored in the response queue; and
transmitting, from the memory device, credit returns at a rate that is based on the quantity of the multiple memory responses stored in the response queue.