CPC G06F 12/1433 (2013.01) [G06F 9/45558 (2013.01); G06F 12/0813 (2013.01); G06F 2009/45583 (2013.01); G06F 2009/45595 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a memory sub-system;
processing circuitry configured to:
generate a first memory access request at a first time to send to the memory sub-system, wherein the first memory access request indicates a first data block;
receive the first data block at a second time from a non-volatile memory via the memory sub-system in response to the first memory access request;
perform a first operation based at least in part on the first data block;
generate a second memory access request at a third time to send to the memory sub-system, wherein the second memory access request indicates a second data block, and wherein a first duration of time between the third time and the first time is less than a duration threshold of time;
in response to the first duration of time between the third time and the first time being less than the duration threshold of time, receive the second data block at a fourth time from buffer memory of a memory controller via the memory sub-system in response to the second memory access request, wherein a second duration of time between the third time and the fourth time is less than a third duration of time between the first time and the second time based on a data transfer speed associated with the buffer memory; and
perform a second operation after the first operation based on the second data block.
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